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ASAHI KASEI
AK2301A
AK2301A
3.3V Single channel CODEC
GENERAL DESCRIPTION The AK2301A is a single channel PCM CODEC for speech processing 8kHz sampling PCM data by DSP. The AK2301A interfaces with 14bit linear data (16bit format). It includes Band limiting filter, A/D and D/A converter, and universal op-amps for construction of the output filter. All functions are provided in small 24pin VSOP package and it is good for reducing the mounting space. PACKAGE - 24pin VSOP Pin to pin 7.9mm x 7.6mm Pin pitch 0.65mm FEATURE
- Single PCM CODEC and filtering - Mute function - PCM interface; 14bits linear data - Long
systems
(16bit format, serial interface) Frame / Short Frame are selected automatically - PCM data rate 256kHz/512kHz - Op-Amp for the external gain adjustment - Dual universal op-amps - Single power supply voltage +3.30.3V - Low power consumption - Small package
BLOCK DIAGRAM
GST VFTN VFTP AMPT
AAF
A/D
PCM I/F VR VFR GSR Internal Main Clock BGREF AMP1 AMP2 SMF AMPR D/A
CODEC Core
DX DR FS BCLK
PLL PLLC MUTEN RSTN TEST1 TEST2 TEST3 AMP2I
TAGND VREF VDD VSS
AK2301A
AMP1O AMP1I AMP2O

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CONTENT
AK2301A
ITEMS -
PAGE
BLOCK DIAGRAM.......................................... 1 PIN CONDITION............................................. 3 PIN FUNCTION............................................... 4 ABSOLUTE MAXIMUM RATINGS..................... 5 RECOMMENDED OPERATING CONDITIONS...... 5 ELECTRICAL CHARACTERISTICS.....................5 PACKAGE INFORMATION............................... 10 PIN ASSIGNMENT.......................................... 11 MARKING...................................................... 11 CIRCUIT DESCRIPTION................................ 12 FUNCTIONAL DESCRIPTION........................... 13 PCM CODEC............................................ 13 PCM INTERFACE....................................... 14 Long Frame / Short Frame......................... 14 MUTE...................................................... 16 RESET SEQUENCE................................... 17 Universal op-amps.................................. 18 APPLICATION CIRCUIT EXAMPLE ................... 19

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PIN CONDITION AC load (MAX.) DC load (MIN.)
Output status (mute)
AK2301A
Pin#
15 16 14 7 8 9 6 19 5 3 2 4 23 22 18
Name
VFTN VFTP GST GSR VFR VR VDD VSS FS BCLK DX DR MUTEN RSTN VREF
I/O
I I O O I O I I O I I I O
Pin type
Analog Analog Analog Analog Analog Analog
Remarks
50pF 40pF
AC load 10k (*1) AC load 8k (*1) AC load 8K (*1) Analog ground
40pF
CMOS CMOS CMOS CMOS CMOS CMOS Analog
50pF
Hi-Z
20 PLLC O Analog
17 TAGND 11 12 13 10 21 24 1 O Analog
- External capacitance 1.0F or more - External capacitance 0.33F4 (Includes temperature characteristic) - External capacitance 1.0F or more - 150uA load max
AMP2I AMP1I AMP1O AMP2O Test1 Test2 Test3
I I O O I I I
Analog Analog Analog Analog CMOS CMOS CMOS 40pF 40pF AC load 8k (*1) AC load 8k (*1)
- Tie to the VSS - Tie to the VSS - Tie to the VSS *1) AC load is a load against AGND. This value includes a feedback resistance of input/output op -amp.

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PIN FUNCTION Pin types NIN: Normal input AIN: Analog input Type Pin# Name 15 VFTN AIN AIN AOUT AOUT AIN AOUT PWR PWR NIN TOUT: Try state output AOUT: Analog output
AK2301A
16 VFTP 14 GST 7 GSR
8 9 6
VFR VR VDD
19 VSS 5 FS
3
BCLK
NIN TOUT NIN NIN NIN
2
DX
4
DR
23 MUTEN 22 RSTN
18 VREF
AOUT AOUT
20 PLLC
17 TAGND AOUT
11 12 13 10 21 24 1
AIN AMP1I AMP2I AMP1O AOUT Output of the universal OP amp AMP2O TEST1 NIN Test pins "H"=test mode Please tie to VSS TEST2 TEAT3
PWR: Power / Ground Function Neagative analog input of the transmit OP amp. Diffelential or single amplifire is composed with the VFTP and the external registers. Transmit gain is defined by the ratio of the external registers. Positive analog input of the transmit OP amp. Output of the transmit OP amp. The external feedback resister is connected between this pin and VFTP. Output of the receive OP amp. Receive gain is defined by the ratio of the external registers. The differential output can be composed with using the VR. Negative analog input of the receive OP amp. Analog output of the D/A convertor equivalent to the received PCM code. Positive supply voltage +3.3V supply Ground (0V) Frame sync input This clock is input for the internal PLL which gerenates the internal system clocks. FS must be 8kHz clock which synchronized with BCLK and do not stop feeding. Bit clock of PCM data interface This clock defines the input/output timing of DX and RX. The frequency of BCLK should be 256kHz or 512kHz and do not stop feeding. Serial output of PCM data The PCM data is synchronized with BCLK. This output remains in the high impedance except for the period in which PCM data is transmitted. Serial input of PCM data The PCM data is synchronized with BCLK. Mute setting pin "L" level forces both A/D, D/A output to mute state. Reset signal input pin Reset operation starts by low input. This pin is used for the initialization at the power up. Please use MUTEN pin together to avoid the popping sound output until the LSI finish the initialaization after the power up.Refer to P.13 Analog ground output External capacitance (1.0F or more) should be connected between this pin and VSS. Please do not connect external load to this pin. PLL loop filter output External capacitance (0.33F40%: Includes temperature characteristic) should be connected between this pin and VSS. Analog ground output for transmitte OP amp 150uA load max. External capacitance (1.0F or more) should be connected between this pin and VSS. This pin is used as an analog ground for transmit OP amp (AMPT). Negative input of the universal OP amp

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ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Power supply voltage Analog/Digital power supply VDD -0.3 Digital input voltage VTD -0.3 Analog input voltage VTA -0.3 Input current (except power supply pins) IIN -10 Storage temperature Tstg -55 Warnig: Exceeding absolute maximum ratings may causepermanent damage. Normal operation is not guranteed at these extermes. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Power supply voltage VDD 3.0 Analog/Digital power supply Ambient operating temperature Ta -40 Frame sync frequency *) FS -1.0% Note) All voltages reference to ground: VSS = 0V *) All the characteristics of the CODEC is definied by 8kHz FS. ELECTRICAL CHARACTERISTICS Typ 3.3 Max 4.6 VDD+0.3 VDD+0.3 10 125
AK2301A
Units V V V
Max 3.6 85 +1.0%
Units V kHz
8
Unless otherwise noted, guaranteed for VDD = +3.3V0.3V, Ta = -40+85, FS=8kHz, VSS=0V DC Characteristics Parameter Power Consumption BCLK=512kHz Output high voltage Output low voltage Input high voltage Input low voltage Input leakage current
Symbol PDD1 VOH VOL VIH VIL ILL
Conditions All output unloaded *1) IOH-1.6mA IOL1.6mA
Min
Typ 10
Max 15
Unit mA V
0.8VDD 0.4 0.7VDD 0.3VDD -10 1.4 1.5 +10 1.6 +10
V V V A V A
Anarog ground output VRG voltage Output leakage current ILT
Tri-state mode
-10
*1) VFTN/P=1020Hz@0dBm0 input, DR=1020Hz@0dBm0 Code input

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PCM INTERFACE (Lomg Frame, Short Frame)
AK2301A
All timing parameters of the output pins are measured at VOH = 0.8VDD and VOL = 0.4V. Input pins are measured at VIH = 0.7VDD and VIL = 0.3VDD. AC Characteristics Parameter FS Frequency BCLK Frequency BCLK Pulse Width (High/Low) (BCLK=32xFS=256kHz) BCLK Pulse Width (High/Low) (BCLK=64xFS=512kHz) Rising/Falling Time: (BCLK,FS0,FS1,DX0,DX1,DR0,DR1) Hold Time: BCLK Low to FS High Setup Time: FS High to BCLK Low Setup Time: DR to BCLK Low Hold Time: BCLK Low to DR Delay Time: BCLK High to DX valid Delay Time: BCLK High to DX High-Z Long Frame Hold Time: 2 period of BCLK Low to FS Low Delay Time: FS or BCLK High, whichever is later,to DX valid 1 FS Pulse Width Low Short Frame Hold Time: BCLK Low to FS Low Setup Time: FS Low to BCLK Low tHBFS tSFBS 60 60 ns Fig2 ns
nd
Symbol fPF fPB tWBH tWBL tWBH tWBL tRB tFB tHBF tSFB tSDB tHBD Note1 Note1 tDBD tDZC
Min -1.0% 1.563 0.781
Typ 8 32FS/ 64FS 1.953 0.977
Max +1.0% 2.344 1.172 40
Unit Ref Fig kHz kHz s s ns ns ns ns ns Fig1, 2
60 60 60 60 60 60
ns ns
tHBFL tDZFL tWFSL
60 60 1
ns ns
BCLK
Fig1
Note1) Measured with 50pF load capacitance and 0.2mA drive.

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Interface Timing
AK2301A
tFB
tRB tWBL
tWBH
1/fPB
BCLK
tSFB tHBFL
FS DX DR
tHBF
tDZFL tDBD MSB 2 3 tSDB MSB 2 3 4 tHBD 4 5 6 7 14 5 6 7 14 tDZC
FS
1/fPF tWFSL
Fig1. Long Frame
tFB
tRB
tWBL
tWBH
1/fPB
BCLK
tSFB tHBFS
FS
tHBF tSFBS tDBD MSB 2 3 tSDB 4 tHBD 4 5 6 7 14 5 tDBD 6 7 14 tDZC
DX DR
MSB
2
3
Fig2. Short Frame

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* The receive and transmit op-amp's characteristics are measured at the 0dB gain. The frequency specifications when FS deviation from 8kHz are as follows:
AK2301A
Used FS x noted frequency specification = Effective frequency specification 8k[Hz]
Absolute Gain Parameter Conditions Analog input level VFTP,VFTN 0dBm0@1020Hz input Absolute transmit gain DX Maximum overload level 3.14dBm0 Analog output level 0dBm0@1020Hz input DR Absolute receive gain VR Maximum overload level 3.14dBm0 Frequency response Parameter Conditions Transmit frequency response Relative to: 0.05kHz 0dBm0@1020Hz 0.06kHz 0.2kHz VFTP,VFTN DX 0.33.0kHz 3.4kHz 4.0kHz Receive frequency response Relative to: 03.0kHz 0dBm0@1020Hz 3.4kHz DR VR 4.0kHz Distortion Parameter Transmit signal to Distortion VFTP,VFTN DX Receive signal to Distortion DR VR Condtions 1020Hz Tone 0dBm0 C-message 1020Hz Tone 0dBm0 C-message 70 75 dB 70 75 dB Min Typ Max Unit Min -0.6 -0.6 Typ 0.531 0.762 0.531 0.762 Max 0.6 0.6 Unit Vrms dB Vrms Vrms dB Vrms
Min 30 26 0 -0.15 0 14 -0.15 0 14
Typ
Max 1.8 0.15 0.8 0.15 0.8
Unit
dB
dB

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Noise Parameter Condtions Idle channel noise AD (*1) C-message VFTP,VFTN DX Idle channel noise DA(*2) C-message DR VR,GSR PSRR VDD=3.3V/66mVop Transmit path f=010kHz PSRR VDD=3.3V/66mVop Receiver path f=010kHz (*1) Analog input is set to the analog ground level (*2) Digital input is set to the +0 CODE Crosstalk Parameter Transmit to receive VFTP,VFTN VR,GSR Receive to transmit DR DX Condtions VFTP,VFTN=0dBm0@1020Hz DR=0-Code DR=0dBm0@1020Hz code level VFTP,VFTN=0 Vrms Min Typ Min Typ 8 5 55 55
AK2301A
Max 13 10 Unit dBrnC0 dBrnC0 dB dB
Max -75 -75
Unit dB dB
Transmit op-amp characteristics:AMPT Parameter Load resistance Load capacitance Gain
Conditions
Min 10 12
Typ
Max 50 6
Unit k pF dB
AC load, Including feedback registance Inverting amplifire
Receive signal output characteristics:VR Parameter Output voltage (AGND level) Load resistance Load capacitance
Conditions
Min 8
Typ 1.5
Max 40
Unit V k pF
PCM +0 code input AC load
Receive op-amp characteristics:AMPR Parameter Load resistance Load capacitance SINAD Gain Output voltage swing
Conditions
Min 8 70 -12
Typ 75 2.15
Max 40 6
Unit k pF dB dB Vp-p
AC load, Including feedback registance 0dB setting, 1020Hz@0dBm0 input VR,GSR differential output With C-message Inverting amplifire DR = 3.14dBm0 digital code input
Universal op-amp characteristics:AMP1,2 Parameter Load resistance Load capacitance SINAD Gain Output voltage swing
Conditions
Min 8 62 -12 2.1
Typ 87 2.25
Max 40 6
Unit k pF dB dB Vp-p 2004/3
AC load, Including feedback registance +6dB setting, 1020Hz@1.125VP-P input 5Hz~30kHz measurment Inverting amplifire +6dB setting, 1020Hz@1.125VP-P input
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PACKAGE INFORMATION 24PIN VSOP
AK2301A
7.80.1
24
13
1.00.2
0.50.2 7.600.20
+0.03 0.17-0.05
5.6
1
12
0.65
0.220.05
0.08
M
010 1.15 1.25 +0.20 0.10
0.08

0.10
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PIN ASSIGNMENT
AK2301A
24PIN VSOP
TEST3 DX BCLK DR FS VDD GSR VFR VR AMP2O AMP2I AMP1I
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
TEST2 MUTEN RSTN TEST1 PLLC VSS VREF TAGND VFTP
VFTN GST AMP1O
TEST1, TEST2 and TEST3 are test pins. Please tie them to the VSS.
MARKING
(1) (2) (3) (4)
1pin sign Date Code: 5digit XXXXX Marketing Code: AK2301A AKM logo
(4) (3)
(1)
AKM AK2301A XXXXX
(2)

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CIRCUIT DESCRIPTION BLOCK AMPT
AK2301A
AMPR
AAF CODEC A/D CODEC D/A SMF BGREF
FUNCTION Op-amp for input gain adjustment. This op-amp is used as an inverting or differential amplifier. Adjusting the gain with external resistors. The resistor should be larger than 10k for the feedback resistor. VFTN: Negative op-amp input. VFTP: Positive op-amp input. GST: Op-amp output. Op-amp for output gain adjustment. This op-amp is used as an inverting amplifier. Adjusting the gain with external resistors. The combined resistor larger than 8k is recommended for the feedback and the output load VFR: Negative op-amp input. GSR: Op-amp output. VR and GSR can be used as the differential output. Integrated anti-aliasing filter which prevents signals around the sampling rate from folding back into the voice band. AAF is a 2 nd order RC active low-pass filter. Converting the analog signal to 14bit PCM data. The band limiting filter is also integrated. Converting the 14bit PCM data from the DR to the analog signal. Output of the D/A converter is fed into the SMF to suppress the high frequency element. Extracts the inband signal from D/A output. It also corrects the sinx/x effect of the D/A output. Provide the stable analog ground voltage using an on-chip band-gap reference circuit which is temperature compensated. The output voltage is 1.5V for 3.3V An external capacitor of 1.0uF or larger should be connected between VREF and VSS to stabilize analog ground (VREF). Please do not connect external load to this pin. TAGND pin is used as the analog ground level output for the AMPT. An external capacitor of 1.0uF or larger should be connected between TAGND and VSS to stabilize analog ground. For the PCM data rate, both 256kHz or 512kHz are available. The 14bit PCM data is input/output by the 2's compliment 16bit serial data format. Two kinds of serial data format (Long Frame/Short Frame) are available. Each data format is automatically detected by AK2301A. PCM data is input to DR pin and output from DX pin. Universal op-amp for the filter of the external voice path. The maximum load is 8k (including the feedback resistor and AC load). These op-amps are assumed as using for the inverting LPF with 20kHz cut off frequency.
PCM I/F
AMP1AMP2

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FUNCTIONAL DESCRIPTIONS
AK2301A
PCM CODEC
- A/D Analog input signal is converted to 14bit PCM data. The analog signal is fed to the anti-aliasing filter (AAF) before the converting PCM data, to prevent signals around the sampling rate from folding back into the voice band. The converted PCM data passes through the band limiting filter which Frequency response is designated in page8, and output from the DX pin with MSB first format. It is synchronized with rising edge of the BCLK. This PCM data is 2's compliment 2digit data and full scale is defined as 3.14dBm0. The analog input of 0.762Vrms is converted to a digital code of 3.14dBm0. - D/A Input PCM data from the DR pin is through the digital filter which Frequency response is designated in page8, and converted analog signal. This analog signal is removed the high frequency element with SMF (fc=30kHz typ) and output from the VR pin. The input PCM data is 2's compliment 2digit data and full scale is defined as 3.14dBm0. When the input signal is 3.14dBm0, the level of the analog output signal becomes 0.762Vrms. - PCM digital code The relation ship between the analog signal and the 14 bit linear code. Signal level 14bit linear CODE (MSB First) + Full scale 01 1111 1111 1111 Peak value of the PCM 0dBm0 CODE 01 0110 0100 1010 PCM 0-CODE 00 0000 0000 0000 - Full scale 10 0000 0000 0000

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AK2301A
PCM Data Interface
AK2301A supports the following 2 PCM data formats - Long Frame Sync (LF) - Short Frame Sync (SF) PCM data is interfaced through the pin (DX, DR). In each case, PCM data is interfaced by the 2's compliment 2digit data with 16bit MSB first format. However, internal CODEC is 14bit format operation, then the lowest 2bits output become to "L" level. For the input, the lowest 2 bits are ignored.
Selection of the interface format
The AK2301A automatically selects the Long Frame/Short frame by means of detecting the length frame signal.
LONG FRAME (LF) / SHORT FRAME (SF)
-Automatic LF/SF detection
AK2301A monitors the duration of the "H" level of FS and automatically selects LF or SF interface format. Period of FS="H" More than 2clocks of BCLK 1clock of BCLK Frame type LF SF
Timing of the interface
16bit PCM data is accommodated in 1 flame (125s) defined by 8kHz frame sync signal. Although there are 4time slot at maximum in 8kHz frame (when BCLK = 512kHz), PCM data for AK2301A occupies first time slot.

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AK2301A
- Frame sync signal FS 8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface. All the internal clock of the LSI is generated based on this FS signal. -Bit clock BCLK BCLK defines the PCM data rate. BCLK rate is 256kHz or 512kHz. This clock must be synchronized with FS.
Long Frame
FS
BCLK
DX
Don't care
1
2
3
4
5
6
7
8
9 10 11 12 13 14 L
L
DR
Short Frame
1
2
3
4
5
6
7
8
9 10 11 12 13 14
Don't care
FS
BCLK
DX
1
2
3
4
5
6
7
8
9 10 11 12 13 14 L
L
DR
Don't care
1
2
3
4
5
6
7
8
9 10 11 12 13 14
Don't care
Important notice!
Please don't stop feeding FS and BCLK. Both FS and BCLK is used as the internal reference clock. LSI does not work when the FS and BCLK are not provided.

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AK2301A
MUTE
The output of the PCM CODEC can be muted by pin control. MUTEN pin MUTEN pin 0 1 Operation Mute Normal DX pin High-Impedance PCM data output VR pin CODEC analog ground CODEC analog output
[DX pin] When the MUTEN pin turns to "L" during the data output, the mute function becomes available at the top of the next FS. [VR pin] When the MUTEN pin turns to "L", 0 code is fed to the D/A converter and VR becomes at analog ground level.

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AK2301A
RESET and Start up sequence
Reset operation starts by low input. This function is used for the initialization at the power up. Please use MUTEN together with RSTN to avoid the popping sound from the output until the AK2301A moves into the stable operation. - Start up sequence (1) After the power on, please set the RSTN pin to low level for 10msec or more. (2) Before the first sequence or less than 250s after the cancellation of reset, please provide the FS and the BCLK. (3) Please set the MUTEN pin to low level during the period of the AK2301A's initialization which is less than 200msec after the FS and the BCLK provided. The CODEC voice path is established by releasing the mute function.
less than250usec 10msec or more 200msec or more
VDD RSTN FS BCLK MUTEN
0.9VDD
(1) (2)
(3)

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AK2301A
Universal op-amps
The op-amps for construction of the external filter. The AMP1(2)I is negative input and the AMP1(2)O is output of the op-amp. - Circuit example Please design output load may become 8k or more. The output load includes a feedback resistor and AC load. These op-amps are assumed to be used for 20kHz max cut off frequency LPF. And please design the gain may become -12~6dB. The following figure shows the circuit example.
C1 R1
AMP1(2)I
R2 C3
C2
AMP1(2)O
Load Z
VSS
Each parameter is calculated as is shown below. LPF cut-off frequency fcL[Hz] fcL=1/(2R2C2) Output load L[] L= R2Z/( R2+Z) Gain A[dB] A=20log (R2/ R1 ) HPF cut-off frequency fcH[Hz] fcH=1/(2R1C1)

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APPLICATION CIRCUIT EXAMPLES
AK2301A
Analog input circuit
GST
20kohm 100pF
Analog output circuit
1uF
VR
1uF
10kohm
VFTN VFTP
100pF 20kohm
10kohm load
1uF
40kohm
VFR
100pF
1uF
10kohm
40kohm
TAGND
1uF 10kohm load
1uF
GSR
VSS
Universal op-amps
1uF 20kohm
Power supply, PLL loop filter capacitor and analog ground stabillization capacitor
VREF
AMP1I
200pF
VREF
40kohm 1uF 10kohm load
1uF
AMP1O
VSS
PLLC
VSS 0.33uF 1uF 20kohm
PLL
AMP2I
200pF VSS
40kohm 1uF 10kohm load
VDD AMP2O
10uF 0.1uF
VSS
VSS

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AK2301A
IMPORTANT NOTICE
l These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. l AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. l Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. l AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. l It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising
from the use of said product in the absence of such notification.

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